Lead RFIC Design Engineer (RF Transceiver) - Bangalore, KA
My client is a semiconductor startup from Bangalore, India, developing a line of low-power AIoT SoC products, bringing AI to the edge on IoT devices.
Their chips are ultra-portable, lowpower SoCs, capable of AI inferencing on the device, with RF connectivity, and a host of analog & digital interfaces for high precision data acquisition.
They provide a full firmware stack that allows the development and deployment of AI/ML applications quickly and easily.
Job Description
The candidate will be involved in the development of next-generation ultra-low power Wi-Fi integrated SoCs targeted for IoT, wearable, and battery-operated applications.
The candidate will design RF and mixed-signal transceiver blocks optimized for power efficiency, small form factors, and multi-radio coexistence.
This role requires strong RF circuit design expertise along with a deep understanding of low power wireless system trade-offs.
The engineer will work across architecture, circuit implementation, layout, silicon validation, and system-level optimization
Engineers are expected to have a strong technical background with a go-getter
attitude.
Primary Responsibilities
Derive RF specifications from system-level requirements including receiver
sensitivity, noise figure, linearity and blocking performance, power consumption
targets, Duty cycling and wake-up latency.
Design, simulate, and optimize analog and RF IC blocks such as amplifiers, mixers, oscillators, filters, low-noise amplifiers (LNAs), and power amplifiers (PAs)
Develop high-performance designs that meet stringent requirements for power,
noise, and linearity
Guide layout engineers on the physical implementation of analog/RF blocks, with an understanding of the impact of parasitics and layout dependencies
Conduct post-layout simulations and resolve layout-related issues to meet
performance and yield targets
Collaborate with test engineers to define test strategies and design-for-test (DFT)
implementations
Support silicon validation and debugging, providing technical expertise to ensure
successful first-pass silicon
Required Qualifications
5–10 years of experience in analog/RFIC design with successful product tape-outs
BTech/MTech/Ph.D. in Electrical Engineering or related field, with a focus on
Analog/RFIC design.
Ability to define chip-level specifications for matching, signal path, spurious
performance, and frequency planning
Strong knowledge of wireless communication fundamentals, noise and linearity
trade-offs, and RF measurement techniques
Proficient in analog/RF circuit design in CMOS technology
Hands-on experience with Cadence Spectre, Mentor Graphics, or similar EDA tools
Solid understanding of matching, noise, stability, and non-linearity in RF circuits
Strong problem-solving skills, attention to detail, and effective communication in a team environment
If you’re interested, please drop an email to premchand.ravella@premsnotes.com